Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory stack structure sometimes referred to as Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductive and dielectric layers. A memory opening is formed through the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory opening with appropriate materials. A straight NAND string extends in one memory opening, while a pipe- or U-shaped NAND string (p-BiCS) includes a pair of vertical columns of memory cells. Control gates of the memory cells may be provided by the conductive layers.
Referring to FIG. 1, a layout of a prior art three-dimensional (3D) NAND chip is illustrated in which the word line decoder circuitry and the bit line decoder circuitry are located in areas that are separate from the area of the array of memory cells. A 3D NAND bank (which is also referred to as a 3D NAND plane or a page) is located a rectangular area. Word line decoder circuitry (which is also referred to as a row decoder circuitry, or a “ROWDEC circuitry”) controls the voltages applied to the word lines of the 3D NAND bank. Staircase regions can be provided adjacent to the 3D NAND bank so that vertical contact via structures to the word lines can be formed in the staircase areas. Metal lines (schematically illustrated as horizontal lines between pairs of a staircase region and a word line decoder circuitry) can provide electrical connection between the word lines of the 3D NAND bank and the word line decoder circuitry. A sense amplifier circuitry (which is also referred to as a bit line decoder circuitry or a “page buffer” circuitry) controls voltage applied to the bit lines (which are schematically illustrated as vertical lines extending over the 3D NAND bank and to the sense amplifier circuitry) controls voltages applied to the bit lines, detects the status of individual memory cells within the 3D NAND bank (for example, during a read operation), and latches the status of the individual memory cells. The word line decoder circuitry can be embodied as two blocks of peripheral device regions located adjacent to the staircase regions, and the sense amplifier circuitry can be located in an area that is 90 degrees rotated from one of the word line decoder circuitry areas to enable connection with all of the bit lines.
The areas of the word line decoder circuitry and the sense amplifier circuitry are not negligible as a fraction of the entire area of the semiconductor chip. The total areas of the word line decoder circuitry and the sense amplifier circuitry can easily exceed 20% of the total chip area, and may exceed 30% of the total chip area for some 3D NAND memory products. The total areas of the word line decoder circuitry and the sense amplifier circuitry as a fraction of the total area of a 3D NAND memory chip is expected to increase even further as the total number of word lines (as implemented as electrically conductive layers in a vertical stack) increases in a high density 3D NAND memory device. Thus, it is desirable to reduce the fraction of the areas that are employed for the word line decoder circuitry and the sense amplifier circuitry over the total chip area in a 3D NAND memory device.